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Low-Power Feature Validation & Bring-Up Engineer

NVIDIA· Engineer, ASIC
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Santa Clara, CA$168k - $264.5kFull-timePosted 4mo ago

About the role

versatile engineer to define and execute low-power silicon validation, system bring-up, and AI-assisted workflows across pre- and post-silicon environments for next-generation AI and accelerated computing platforms.

Responsibilities

  • Define the Power & Performance validation strategy across product lines, including power targets, rail budgets, and low-power feature validation methodologies.
  • Build intelligent workload characterization frameworks using telemetry, behavioral clustering, and AI-assisted analytics to improve validation coverage and expose power-state and data-path issues earlier.
  • Define instrumentation, counters, telemetry frameworks, and firmware hooks to support scalable silicon observability, automated validation, and AI-powered debug workflows prior to tapeout.
  • Bring up and validate system-level low-power features across pre-silicon and post-silicon environments using automation, data-driven validation methodologies, and generative AI-assisted debug techniques.
  • Develop AI/ML-assisted infrastructure for telemetry analysis, anomaly detection, predictive validation analytics, workload optimization, automated triage, and cross-generation debug correlation.
  • Partner with architecture, firmware, DV, HSIO, system integration, and data infrastructure teams to build scalable validation pipelines, dashboards, and modern workflows for next-gen silicon platforms.
  • Support manufacturing and customer-facing teams in resolving production and feature issues using telemetry-powered insights, automated analytics, and scalable debug methodologies.
  • Work across hardware, software, firmware, and platform teams to drive low-power feature readiness from early architecture definition through silicon bring-up, validation, and product release.

Qualifications

  • BS/MS in EE, CE, CS, Systems Engineering, or equivalent experience.
  • 10+ years of experience in silicon characterization, low-power feature validation, system integration, or post-silicon productization.
  • Strong understanding of silicon power behavior, Windows/Linux low-power states, firmware interactions, power/performance tradeoffs, and system-level validation methodologies.
  • Experience building scalable automation, telemetry analytics, or AI-assisted engineering workflows for silicon validation, debug, or productization.
  • Strong EE fundamentals, including digital design, computer architecture, power analysis, statistics, and scripting/programming skills.
  • Hands-on experience with silicon bring-up, lab validation, debug methodologies, and hardware lab instrumentation.
  • Familiarity with AI/LLM-assisted engineering workflows, intelligent automation frameworks, telemetry analytics, or data-driven debug infrastructure.

Skills

Required:Power and performance validationTelemetry analyticsAI/ML-assisted workflowsAutomation framework developmentSystem bring-up

Benefits

  • equity
  • comprehensive benefits package
Last updated Sep 25, 2026. Interested? Apply on the company site.

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