Senior DFT - Silicon Validation Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA$168k - $310.5kFull-timePosted 4mo ago
About the role
Senior DFT - Silicon Validation Engineer in NVIDIA's Design-for-Test Engineering team, focusing on end-to-end DFT architecture, silicon validation, and test strategies to accelerate post-silicon bring-up, ATE validation, and yield ramp for complex SoCs.
Responsibilities
- Collaborate with multi-functional teams to drive silicon validation of NVIDIA's chips.
- Drive end-to-end DFT architecture and methodologies to accelerate post-silicon bring up and characterization.
- Collaborate across functions to define next-generation test strategies for ATE for the product roadmap.
- Lead early silicon validation for complex SoC or equivalent experience.
- Plan from architecture and development, perform chip validation on ATE, debug test content, and analyze silicon behavior under various operating conditions.
- Identify failure root causes and collaborate with a multi-functional team to ensure a strong production ramp.
- Validate and ramp up yield for chips, impacting NVIDIA's technological advancements.
Qualifications
- BSEE (or equivalent experience) with 8+ years, or MSEE with 5+ years, or PhD with 3+ years in DFT or related domains
- Expertise in silicon debug and bring-up & productization of DFT features
- Demonstrated leadership in driving yield ramp and waste reduction for multiple products
- Hands-on experience in pre-silicon validation for various DFT features
- Outstanding written and oral communication skills
- Strong programming and scripting skills in Perl, Python, or Tcl
Skills
Required:DFTSilicon debug and bring-upPre-silicon validationYield ramp leadershipCommunicationProgramming/scripting
Benefits
- Equity and benefits (as stated)
- Competitive salaries
- Comprehensive benefits package
Last updated Oct 9, 2026. Interested? Apply on the company site.
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