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Senior Digital Design Engineer - High-Speed I/O and Photonics

NVIDIA· Engineer, ASIC Mixed Signal Design
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Santa Clara, CA$136k - $218.5kFull-timePosted 4mo ago

About the role

Senior digital design engineer focusing on high-speed I/O, DSPs, and silicon photonics IPs within NVIDIA’s mixed-signal high-speed I/O group. Responsible for frontend and backend design, micro-architecture definitions, calibration algorithms, RTL/firmware development, PPA trade-offs, and silicon bring-up.

Responsibilities

  • Engage in frontend development for high-speed DSPs, silicon photonics IPs, and chips.
  • Define chip-level features, programming model and application interface definitions.
  • Collaborate with analog designers and system architects to develop micro-architecture specifications, calibration and adaptation algorithms, translated into RTL and firmware designs.
  • Backend design: define and enforce synthesis constraints, drive timing closure.
  • Evaluate PPA trade-offs based on synthesis and place-and-route feedback.
  • Post-silicon: participate in silicon bring-up, build testing scripts for debugging, characterization, performance tuning, and production.
  • Collaborate with cross-functional teams to ensure successful production.

Qualifications

  • B.S. or M.S. degree in Electrical Engineering or equivalent experience.
  • 5+ years of experience in high-speed digital design, proficient with front-end design flow and tools.
  • Deep understanding of Verilog or SystemVerilog, logic design concepts, and typical structures.
  • Good understanding of design for test, timing constraints, and static timing analysis.
  • Experience with industry verification methodologies, such as UVM.

Skills

Required:Verilog/SystemVerilogDigital design conceptsDesign for test, timing constraints, STAUVM verification

Benefits

  • Equity
  • Benefits as per NVIDIA policy (link provided in job description)
Last updated Jun 26, 2026. Interested? Apply on the company site.

About NVIDIA

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