SOC Clock Distribution Engineer
NVIDIA· Engineer, ASIC
Hybrid (Tel Aviv), Hybrid (Yokneam)full-timePosted 4mo ago
About the role
SOC level clock design engineer for NVIDIA's System-On-Chip group, focusing on clock distribution optimization, physical design integration, and interaction with multiple teams to enable optimized SOC production.
Responsibilities
- Designing and implementing SOC level clock requirements
- Daily work involves aspects of chip level design, including partitioning, CDC, trial synthesis, design quality checks
- Be exposed and work on a variety of functional and structural challenges. Including functional debug, physical design readiness, resolve design quality issues
Qualifications
- B.SC. in Electrical Engineering/Computer Engineering.
- 3+ years of confirmed experience in chip design
- Hands-on physical design skills in clock distribution in tight multi power and timing/layout constrained products.
- Proficiency in at least one common scripting language like perl, python, bash, Tcl.
- Phenomenal teammate.
Skills
Required:clock distributionpartitioningcdc (clock domain crossing)trial synthesisdesign quality checksscripting
Last updated Jun 26, 2026. Interested? Apply on the company site.
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