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Principal Solutions Architect – Semiconductor Test

NVIDIA· Engineer, Test
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Santa Clara, CA$216k - $345kFull-timePosted 4mo ago

About the role

Senior individual contributor role defining and leading the technical strategy for semiconductor test across wafer and package test, partnering with multiple engineering and manufacturing teams to scale test infrastructure and embed data-driven intelligence throughout the test lifecycle.

Responsibilities

  • Define the comprehensive test development strategy across wafer-level (probe/ATE) and package/final/qual test for new and existing product families.
  • Lead architectural trade-off decisions on test coverage, test time, cost of test, and quality escapes across the full test flow.
  • Establish architectural guidelines for the test program, Test Methods/Class structure, modularity, and reuse across ATE platforms (Advantest, Teradyne, etc.).
  • Serve as the senior liaison between build and test engineering for DFT architecture decisions — scan, BIST, JTAG, boundary scan, and embedded compression.
  • Influence SoC and IP build reviews to ensure testability, observability, and debug-ability
  • Drive adoption of AI/ML techniques for yield learning, outlier detection, predictive binning, and test time optimization.
  • Define and maintain test roadmaps aligned to device technology roadmaps and manufacturing scale targets.
  • Mentor senior and principal test engineers; cultivate technical standards and guidelines across the test organisation.
  • Engage with ATE vendors, test IP providers, and industry consortia (SEMI, JEDEC, IEEE) on emerging standards and technology directions.

Qualifications

  • 15+ years of hands-on semiconductor test engineering experience within a fab, IDM, or OSAT environment.
  • Extensive knowledge in at least three areas: ATE platform architecture, test program development, DFT methodology, yield analysis, or test data/ML analytics.
  • Skilled in leading ATE platforms such as Advantest V93000, Teradyne UltraFLEX/ETS, or similar systems.
  • Strong background in DFT architectures — scan compression, MBIST, LBIST, JTAG, and related methodologies.
  • Experience with mixed-signal, RF, or high-speed I/O test is highly valued.
  • Proficiency in test-related scripting and automation (Python, Perl, C++, or platform-native languages).
  • Proven ability to lead multi-site technical initiatives involving multi-functional teams and influence without direct authority.
  • MSEE, MSCE, MSCS, or related field (or equivalent experience).

Skills

Required:ATE platform architectureDFT methodologyyield analysistest data/ML analyticsscripting

Benefits

  • equity
  • benefits (as per company offerings)
  • competitive salaries and generous benefits package
Last updated Jun 26, 2026. Interested? Apply on the company site.

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