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ASIC Formal Verification Engineer, TPU Compute

Google· AI and Infrastructure - TPU Compute / Formal Verification
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Sunnyvale, CA, USA$163k - $237kFull-timePosted 4mo ago

About the role

ASIC Formal Verification Engineer role focused on verifying complex digital designs with emphasis on TPU architecture and its integration within AI/ML-driven systems for data center accelerators.

Responsibilities

  • Define and drive the formal verification sign-off approach across complex IP and SoC designs, utilizing advanced formal techniques.
  • Architect, develop, and deploy reusable formal testbenches, methodology flows, and high-coverage SystemVerilog Assertions (SVA) suites across multiple designs and projects.
  • Collaborate with architecture and design teams to translate complex system and IP specifications into comprehensive formal verification test plans.
  • Maintain and enhance continuous integration, regression flows, and dashboarding to provide formal verification status and sign-off metrics.
  • Guide logic designers and verification engineers to effectively incorporate formal methods into their workflows.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 8 years of experience in silicon development or ASIC/SoC design.
  • Experience with SystemVerilog Assertions (SVA) and formal verification methods.

Skills

Required:Formal verificationSystemVerilog Assertions (SVA)

Benefits

  • Learn more about benefits at Google (link provided in description).
Last updated Oct 23, 2026. Interested? Apply on the company site.

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