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Senior Full Chip Layout and Physical Verification CAD Engineer

NVIDIA· Engineer, ASIC
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Hybrid (Yokneam), Hybrid (Tel Aviv)Full-timePosted 4mo ago

About the role

Senior Physical Design role focused on full-chip layout and physical verification for networking silicon, delivering high-speed, low-latency chips. Involves developing methodologies, supporting tapeout, and ensuring quality convergence across multiple projects.

Responsibilities

  • Develop full-chip physical design methodologies, Physical Verification development and support through all projects, and tapeout activities for networking chips and SoCs.
  • Work closely with Full Chip Layout owners, block owners, and project managers to assure high quality and timely convergence.
  • Come up with unique and creative solutions to state-of-the-art FCL physical design problems needed for our chips.
  • Run, debug, and approve Physical Verification flows across multiple projects, ensuring adherence to high standards.
  • Participate in and develop flow and tool methodologies for full-chip physical design verification across multiple projects.

Qualifications

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience)
  • At least 5+ years of hands-on full-chip layout and Physical Verification experience
  • Strong background in Physical Verification methodology including DRC / LVS / ANT / ERC / DFM in advanced process nodes
  • Proficiency in Python, Tcl, Shell, Make scripting
  • Experience in Linux environments
  • AI tools orientation or willingness to learn
  • Familiarity with physical build EDA tools (Synopsys ICC2/FC, Cadence Innovus)
  • Familiarity with Physical Verification tools (Synopsys ICV, Siemens Calibre)
  • Self-motivation, attention to detail, and good interpersonal skills

Skills

Required:Full-chip layoutPhysical Verification (DRC/LVS/ANT/ERC/DFM)PythonTclShellLinuxEDA tools (Synopsys ICC2/FC, Cadence Innovus)EDA tools (Synopsys ICV, Siemens Calibre)
Last updated Jul 3, 2026. Interested? Apply on the company site.

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