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Senior Implementation Methodology Engineer

NVIDIA· Engineer, ASIC
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Santa Clara, CA$168k - $264.5kfull-timePosted 4mo ago

About the role

NVIDIA is seeking a hands-on, technical leader to own synthesis methodology development in the RTL2GDS pipeline for advanced-node CPU builds. The role combines physical design methodology, data-driven optimization, and scalable automation to improve PPA across the RTL2GDS flow, partnering with architecture, RTL, DFT, physical build, and sign-off teams.

Responsibilities

  • Own and continuously improve the end-to-end RTL2GDS implementation methodology — covering synthesis, place & route, CTS, and equivalence checking — for advanced-node CPU builds.

Qualifications

  • BS or MS in Electrical Engineering, Computer Engineering, Computer Science, or related field, or equivalent experience.
  • 6+ years of hands-on proven experience in ASIC implementation methodology and EDA tool/flow development.
  • Deep, practical expertise in the complete RTL2GDS flow: synthesis, DFT, floorplanning, placement, CTS, routing, and MCMM STA.
  • EDA Tool Proficiency: Power user of synthesis and place-and-route tools from Synopsys (DC/FC, ICC2, PrimeTime) and/or Cadence (Genus, Innovus, Tempus).
  • Strong scripting proficiency in Python, TCL, Perl, and/or Make for flow automation and analysis.
  • Demonstrated ability to drive complex, cross-functional technical initiatives.

Skills

Required:RTL2GDS flowEDA toolsPythonTCL

Benefits

  • equity
  • comprehensive benefits package
  • NVIDIA benefits website
Last updated Jul 3, 2026. Interested? Apply on the company site.

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