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Senior Power Integrity Co-Design Engineer

NVIDIA· Engineer, ASIC
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Santa Clara, CA$136k - $264.5kfull-timePosted 4mo ago

About the role

Senior Power Integrity Co-Design Engineer responsible for architecting and delivering di/dt mitigation across silicon, package, board, and platform; translating noise targets into shipped specifications and feeding silicon findings back into next-generation design.

Responsibilities

  • Architect voltage-noise mitigation across the full stack — silicon, package, board, platform — and own the codesign trade-offs between them.

Qualifications

  • BS / MS / PhD in EE, CE, or related (or equivalent experience).
  • 5+ years in silicon power integrity, voltage noise, or PDN.
  • Deep expertise in at least one of: di/dt analysis and mitigation, voltage droop, PDN design (die + package + board), transient noise, decap budgeting, voltage regulator response.
  • Hands-on silicon experience: bringup, characterization, correlation. You're comfortable on a bench with scopes, probes, DAQ — and in front of a simulator.
  • Strong Sim-to-Si correlation instincts.
  • System-level objectivity.
  • Multi-functional collaboration in a matrixed environment.
  • Spec rigor.

Skills

Required:di/dt analysis and mitigationvoltage noise / PDN designtransient noise modelingSim-to-Si correlation

Benefits

  • equity
  • generous benefits package
Last updated Sep 25, 2026. Interested? Apply on the company site.

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