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Memory Mask Design Engineer

NVIDIA· Engineer, Mask Design
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Bengalurufull-timePosted 4mo ago

About the role

Memory Mask Design Engineer responsible for implementing IC layouts for high-speed digital memory circuits in advanced CMOS processes, delivering digital memory layouts, and applying best layout practices within the Full Custom Memory group.

Responsibilities

  • Implement IC layout of innovative, high-performance, high-speed CMOS integrated circuits in foundry CMOS process nodes in 3nm, 5nm, 7nm and lower nodes following industry standard methodologies.
  • Deliver layouts for Full Custom Memory group specializing in digital Memory circuits.
  • IP layout will comprise of significant digital components.
  • Adopting and putting in place the best layout practices/methodology for composing digital Memory layouts
  • Follow company procedures and practices for IC layout activities.

Qualifications

  • B.E/B Tech. / M Tech in Electronics or equivalent experience with 2+ Years of proven experience in Memory layout in advanced CMOS process.
  • Detailed knowledge of industry standard EDA tools for Cadence.
  • Experience with layout of high-performance memories of various types.
  • Knowledge of Layout basics including the various types of bitcells, Decoder, LIO etc. (matching devices, symmetrical layout, signal shielding)
  • Experience with floor planning, block level routing and macro level assembly.
  • Detailed knowledge of top level verification including the EM/IR quality checks and detailed knowledge of layout dependent effects including LOD, Dummification, fills etc.

Skills

Required:Memory layoutCadence (EDA tools)Floor planningLayout verification
Last updated Jun 26, 2026. Interested? Apply on the company site.

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