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Senior Signal Integrity Engineer – LPU Packaging

NVIDIA· Engineer, ASIC Signal Integrity
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Santa Clara, CA$168k - $264.5kFull-timePosted 4mo ago

About the role

Senior SI Engineer focused on high-speed SerDes channel design and SI analysis across die, package, board, and system interfaces for advanced packaging technologies in HPC/data center platforms.

Responsibilities

  • Lead signal integrity design and analysis for high-speed SerDes channels across die, package, board, connector, socket, and cable interfaces
  • Develop and execute simulation flows for advanced packaging technologies, including 2.5D, 3D, and multi-die integration, with focus on channel loss, discontinuities, return path behavior, and crosstalk
  • Build and optimize chip-package-board co-simulation methodologies for next-generation HPC and data center systems
  • Drive SI modeling and design optimization for package escapes, vias, breakouts, interposers, substrates, sockets, and other critical channel structures
  • Perform pre-layout and post-layout signal integrity analysis, create design guidelines, and review layouts to ensure electrical performance targets are met
  • Correlate simulation with lab measurements using TDR, VNA, oscilloscope, and related measurement techniques to improve model accuracy and signoff confidence
  • Work closely with ASIC, package, board, mechanical, thermal, and validation teams to co-optimize electrical performance across the full product stack
  • Support interface bring-up, debug, and margin analysis, and help translate correlation learnings into improved design methods and reusable flows
  • Automate analysis, data processing, and visualization to improve productivity and scale SI methodology across multiple programs

Qualifications

  • BS, MS, or PhD in Electrical Engineering or equivalent experience
  • 8+ years of industry experience in signal integrity, high-speed interconnect design, or related hardware development roles
  • Strong background in electromagnetics, transmission line theory, channel modeling, and high-speed serial link behavior
  • Proven experience with high-speed SerDes design and analysis for advanced packaging and/or large-scale system applications
  • Hands-on experience with industry-standard SI tools such as Ansys HFSS, SIwave, Cadence Sigrity, ADS, HSPICE, or equivalent
  • Experience building and using channel models, S-parameters, IBIS-AMI based flows, and time/frequency-domain analysis techniques
  • Strong understanding of NRZ and PAM4 signaling, equalization techniques, jitter/noise mechanisms, and end-to-end channel budgets
  • Experience with simulation-to-measurement correlation and lab-based model validation using VNA, TDR, and high-speed scope measurements
  • Ability to work effectively across cross-functional teams and drive technical decisions in a fast-moving product environment

Skills

Required:High-speed SerDes design and analysisElectromagnetics and transmission line theory

Benefits

  • You will also be eligible for equity and benefits (per company policy)
Last updated Sep 4, 2026. Interested? Apply on the company site.

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