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Silicon RTL Design Engineer, PhD, Google Cloud

Google· Google Cloud
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Bengalurufull-timePosted 4mo ago

About the role

Position focused on shaping the future of AI/ML hardware acceleration by driving TPU technology, with responsibilities spanning architecture, design, verification, and collaboration across hardware and software teams to deliver high-performance, power-efficient TPUs for AI/ML workloads.

Responsibilities

  • Revolutionize Machine Learning (ML) workload characterization and benchmarking, and propose capabilities and optimizations for next-generation TPUs.
  • Develop architecture specifications that meet current and future computing requirements for AI/ML roadmap. Develop architectural and microarchitectural power/performance models, microarchitecture and RTL designs and evaluate quantitative and qualitative performance and power analysis.
  • Partner with hardware design, software, compiler, ML model and research teams for effective hardware/software codesign, creating high performance hardware/software interfaces.
  • Develop and adopt advanced AI/ML capabilities, drive accelerated and efficient design verification strategies and implementations.
  • Use AI techniques for faster and optimal physical design convergence-timing, floor planning, power grid and clock tree design, etc. Investigate, validate, and optimize DFT, post-silicon test, and debug strategies, contributing to the advancement of silicon bring-up and qualification processes.

Qualifications

  • PhD degree in Electronics and Communication Engineering, Electrical Engineering, Computer Engineering, a related technical field, or equivalent practical experience
  • Experience in programming languages (e.g., C++, Python, Verilog), Synopsys, Cadence tools.
  • Experience with accelerator architectures and data center workloads.

Skills

Required:PhD in Electronics and related fieldProgramming languages (C++, Python, Verilog)Synopsys, Cadence toolsArchitecture and microarchitecture modelingHardware/software co-designDesign verificationDFT, post-silicon test and debug
Last updated Oct 23, 2026. Interested? Apply on the company site.

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