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Senior Verification Engineer - ARM Fabric Unit Level

NVIDIA· Engineer, Verification
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Hybrid (Bengaluru, India), Hybrid (Hyderabad, India)Full-timePosted 3mo ago

About the role

Senior verification engineer focused on HSIO IP unit-level verification for automotive Tegra chips. Develop UVM-based verification environments for an ARM-based distributed fabric, coordinating with architects, designers, FPGA, and post-silicon teams to ensure robustness of the unit.

Responsibilities

  • Architect the testbenches and craft verification environment using SV and UVM methodology
  • Define test plans, tests and verification infrastructure for modules, clusters and systems
  • Build efficient and reusable bus functional models, monitors, checkers, and scoreboards
  • Implement functional coverage and coordinate the verification closure process for the unit
  • Work with architects, designers, FPGA, and post-silicon teams to ensure that your unit is robust

Qualifications

  • BTech or MTech in ECE, EE, CSE, or an equivalent degree
  • 4+ years of demonstrated ability in verification closure of complex units, sub-systems, or SOC level verification
  • Proven experience in ARM architecture and protocols (AXI, AHB and APB)
  • Experience in SV and UVM verification methodologies
  • Good debugging and analytical skills with exposure to industry-standard verification tools for simulation and debug
  • Good interpersonal skills, ability to work as a diligent teammate, and excellent communication skills to collaborate with cross-cultural global teams and work in a matrix organization

Skills

Required:UVMSystemVerilogARM architecture and protocols

Benefits

  • Competitive salaries
  • Comprehensive benefits package
  • Accommodation for disabilities during application/interview process
Last updated Jul 3, 2026. Interested? Apply on the company site.

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