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Senior SoC Subsystem and I/O Architect - LPU

NVIDIA· Architect
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Remote$184k - $287.5kFull-timePosted 3mo ago

About the role

Senior SoC Subsystem & I/O Architect responsible for defining high-level SoC subsystem architecture for NVIDIA’s LPU products, focusing on uncore IO, memory, boot/reset, safety, fault tolerance, power regulation, and platform initialization across PCIe/CXL, NVLink, UCIe, AXI/CHI, NoC fabrics, and related subsystems.

Responsibilities

  • Define high-level SoC subsystem architecture for LPU products.
  • Convert LPU product requirements into architectural specifications for uncore, IO, memory, firmware-facing, boot, reset, safety, fault tolerance, diagnostic, and power regulation subsystems.
  • Collaborate with IP teams to develop detailed build documents for PCIe/CXL, NVLink/NVLink-C2C, UCIe, AXI/CHI, NoC fabrics, memory controllers, coherency blocks, MMUs/IOMMUs, boot, reset, and associated SoC infrastructure.
  • Specify subsystem behavior encompassing enumeration, capability discovery, configuration flows, sequence control of memory operations, data consistency, address mapping, interrupt handling, virtualization, error handling, and firmware/software-visible controls.
  • Build or guide functional and architectural models from specifications, using C++, SystemC, Python, or similar languages.
  • Use models to validate architecture intent, subsystem behavior, configuration sequences, and IP interactions before RTL or silicon is available.
  • Drive tradeoffs across bandwidth, latency, power, area, timing, scalability, reliability, security, debuggability, and software usability.
  • Review IP specifications, subsystem architecture documents, model behavior, verification plans, and validation strategies.
  • Collaborate with architecture, IP, firmware, software, RTL, verification, platform, and post-silicon teams to bring architecture decisions to completion.

Qualifications

  • BS, MS, or PhD in Electrical Engineering, Computer Engineering, Computer Science, or equivalent experience.
  • 8+ years of proven experience in SoC architecture, subsystem architecture, IO architecture, interconnect architecture, GPU/CPU architecture, accelerator architecture, or high-performance systems.
  • Strong understanding of SoC architecture and uncore subsystem development.
  • Extensive understanding of IO and interconnect cores including PCIe, CXL, NVLink, NVLink-C2C, UCIe, AXI, CHI, or NoC fabrics.
  • Experience working from product requirements to architecture requirements and IP/subsystem specifications.
  • Experience crafting functional models, architectural models, golden models, or C/SystemC models from architecture specifications.
  • Solid grasp of memory ordering, coherency, address translation, interrupts, virtualization, MMUs/IOMMUs, enumeration, configuration, and error management.
  • Solid knowledge of boot, reset, firmware handoff, capability discovery, security, RAS, debug, and power-management architecture.
  • Strong communication abilities and capability to harmonize architecture decisions across IP, firmware, software, verification, and product groups.

Skills

Required:SoC architectureUncore and IO subsystemsMemory systems and coherencyModeling and simulation
Nice to have:Boot/reset/firmware architecture

Benefits

  • Equity and benefits (as per company offerings).
  • Competitive salaries and comprehensive benefits package.
Last updated Aug 7, 2026. Interested? Apply on the company site.

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