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GPU Core Pipeline IP Verification Engineer

NVIDIA· Engineer, ASIC
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Bengalurufull-timePosted 3mo ago

About the role

Verification Engineer to verify the design and implementation of GPU core pipeline control subsystems and IP-level ASIC verification using UVM methodologies. On-site in Bengaluru, India.

Responsibilities

  • Verify graphics and compute features within an IP at the ASIC level, including design, architecture, golden models, and micro-architecture.
  • Develop test plans, tests, and verification infrastructure using UVM methodology to ensure functional and code coverage of RTL.
  • Collaborate with HW architects and designers to make implementation decisions.
  • Work with architects, designers, and verification teams to complete tasks.

Qualifications

  • B.Tech./M.Tech with 2+ years of relevant experience
  • Familiarity with Verilog, C++ and OOP concepts
  • Experience in verification and test planning at Unit level
  • Experience in developing and working in functional coverage based constrained random verification environments
  • Good understanding of computer architecture concepts
  • Strong technical fundamentals with superior analytical and problem-solving skills
  • Knowledge in SystemVerilog or similar HVL; experience with verification methodologies like UVM/VMM is highly desirable
  • Exposure to industry standard verification tools for simulation and debug

Skills

Required:VerilogC++Object-Oriented Programming (OOP)Constrained Random VerificationFunctional CoverageDigital ArchitectureDebuggingCommunication & teamwork
Nice to have:SystemVerilog / HVLUVM / VMM
Last updated Jul 10, 2026. Interested? Apply on the company site.

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