Senior DFT Power Methodology Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA$168k - $264.5k + equityFull-timePosted 3mo ago
About the role
Senior DFT Power Methodology Engineer at NVIDIA focusing on Design-for-X (DFT) power, thermal and voltage noise methodologies, with emphasis on low power and thermal solutions for manufacturing tests, post-silicon data analysis, and applying Applied ML & Gen AI to DFT methodologies.
Responsibilities
- As a senior member in our team, you will work on innovating in the DFT Power, Thermal & Voltage Noise Methodology areas.
- This will include working on groundbreaking low power & thermal solutions for our manufacturing tests to be enabled at conditions that push the boundaries for our datacenter GPUs.
- Partner with multi-functional teams including Product Development & Power Architecture, implementing brand-new methodologies on hard-to-solve problems for improving our outgoing quality of chips.
- You will work on post-silicon data analysis for power to architect the next-gen solutions.
- In addition, you will help develop and deploy DFT methodologies for our next generation products using Applied ML & Gen AI solutions.
- Help mentor junior engineers on test designs and trade-offs including cost and quality.
Qualifications
- BSEE (or equivalent experience) with 12+ years, MSEE with 10+ years, or PhD with 6+ years of experience in DFT design & power
- Understanding of fundamental DFT topics and VLSI areas of power, timing & voltage noise
- Experience in Power Analysis, Thermal Analysis & IR Drop tools is a plus
- Experience in application of AI for EDA-related problem-solving is a plus
- Excellent knowledge in using statistical tools for data analysis & insights
- Good exposure to multi-functional areas including RTL & clocks design, STA, place-n-rout e and power
- Experience in Silicon debug and bring-up on the ATE or SLT platforms
- Be able to think like a programmer so that this can be translated into action using AI Coding harnesses
Skills
Required:DFT design & powerStatistical data analysisProgramming mindset for AI coding harnesses
Nice to have:Power AnalysisThermal AnalysisIR Drop toolsApplied ML & Gen AI for EDARTL & clocks design, STA, place-n-routeSilicon debug & bring-up on ATE/SLT
Benefits
- equity
- comprehensive benefits package
Last updated Oct 23, 2026. Interested? Apply on the company site.
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