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Senior Mask Design Engineer - Hardware

NVIDIA· Engineer, Mask Design
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Hybrid (Hsinchu), Hybrid (Taipei)full-timePosted 3mo ago

About the role

Senior Mask Layout Design Engineer responsible for physical layout of mixed-signal functions in sub-micron CMOS technologies, collaborating with mixed-signal design engineers, performing floor planning, custom layout, and verification to design rules and schematics for NVIDIA’s latest generation chiplet interface projects.

Responsibilities

  • Perform physical layout for mixed-signal functions like top level, high speed datapaths and high-speed clocking designs in state-of-the-art sub-micron CMOS technologies using Cadence tools.
  • Work closely with mixed-signal design engineers to customize designs for integration in VLSI products.
  • Take part in floor planning, custom layout and verifying against design rules and schematics.

Qualifications

  • BSEE or equivalent experience. Minimum of 5+ years industry experience in Mask and Layout Design.
  • Working independently on creating layout with excellent quality
  • Deep understanding and previous experience for FinFET technology
  • Authority with Cadence custom circuit design tools - particularly virtuoso
  • Able to handle fast-paced project and iterate quickly based on designer’s feedback
  • Team player with good interpersonal skills, enthusiasm, and positive energy
  • Scripting languages like Perl, Python, Skill, etc. is a plus
  • Knowledge of DRC and LVS checking flows, ability to customize decks

Skills

Required:Physical layout designCadence VirtuosoFinFET technologyDesign rule checks (DRC) and LVS
Last updated Jul 24, 2026. Interested? Apply on the company site.

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