ASIC Design Engineer - New College Grad 2026
NVIDIA· Engineer, ASIC
Santa Clara, CA$100k - $166.8kfull-timePosted 3mo ago
About the role
Logic Design Engineer position on the CPU Logic Design Team focusing on on-chip interconnect, coherency, and last-level caches, with responsibilities across RTL coding, synthesis, timing closure, verification collaboration, and implementation.
Responsibilities
- Own and deliver a specific unit on the chip as part of the core CPU team
- Write high performance and low power RTL
- Perform synthesis and timing closure
- Collaborate with verification to verify unit correctness
- Work with implementation to meet timing, area, performance, and power goals
- Assist with timing closure of super units
- Document design and assist with lab bring-up and debugging (DFT, ECO, floor-planning referenced in description)
Qualifications
- Recent graduate with a BS or MS in Electrical Engineering, Computer Engineering or Computer Science (or equivalent)
- Experience in processor or other related high performance semiconductor designs
- Verilog expertise and deep understanding of ASIC design flow including RTL design, verification, logic synthesis, prototyping, DFT, timing analysis, floor-planning, ECO, bring-up & lab debug
- Effective communication and interpersonal skills; mentoring juniors a plus
- Strong background in computer architecture, cache coherency or high speed interconnects
Skills
Required:VerilogASIC design flowComputer architectureCommunication
Benefits
- Eligibility for equity and benefits
Last updated Jul 24, 2026. Interested? Apply on the company site.
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