RTL Power Optimization Engineer – New College Grad 2026
NVIDIA· Engineer, ASIC
Santa Clara, CA$116k - $189.8kfull-timePosted 3mo ago
About the role
Role focused on pre-silicon RTL and architecture power optimization for NVIDIA GPUs and Networking chips, collaborating with cross-functional teams to analyze, optimize, and implement power reduction techniques using RTL, AI/ML methods, and power analysis tools.
Responsibilities
- Use internally developed tools and industry standard pre-silicon gate-level and RTL power analysis tools, to help improve product power efficiency.
- Use artificial intelligence to deliver RTL and/or Architecture Power optimization solutions.
- Develop and share best practices for performing pre-silicon power analysis.
- Perform comparative power analysis, to spot trends and anomalies, that warrant more scrutiny.
- Interact with architects and RTL designers to help them interpret their power data and identify power bugs; drive them to implement fixes.
- Select and run a wide variety of workloads for power analysis.
- Prototype a new architectural feature in Verilog and analyze power.
Qualifications
- Pursuing or recently completed a MS or PhD in Electrical Engineering, Computer Engineering, or related fields with coursework or experience in AI, Digital Design and VLSI concepts (or equivalent experience).
- Understanding of RTL power optimization fundamentals, including switching activity, clock/enable efficiency, and common low‑power design patterns at the RTL level.
- Knowledge of backend flows such as logic synthesis and place‑and‑route, and how RTL decisions impact post‑layout power and timing.
- Familiarity with RTL implementation of low‑power techniques (e.g., clock gating, operand isolation, power gating strategies, multi‑VT usage) and their trade‑offs.
- Exposure to industry power analysis tools such as PowerArtist, PrimeTime PX, or equivalent, including running power analysis and interpreting reports to guide design changes.
- Strong Python programming skills for building automation scripts, data pipelines, and AI/ML‑driven analysis flows for RTL power optimization.
- Coursework and/or hands‑on experience in Machine Learning and Artificial Intelligence, with ability to apply ML techniques to EDA and silicon power problems.
- Previous experience debugging RTL or gate‑level power anomalies by tracing logic cones, examining activity/toggle data, and identifying root‑cause structures or scenarios.
- Strong written and verbal communication skills to document methodologies, present power findings, and explain AI/ML‑based insights to both design and tools teams.
Skills
Required:RTL power optimizationPower analysis toolsPythonMachine Learning / AI for EDAVerilogDebugging RTL power issues
Benefits
- equity
- health benefits (see company benefits link)
Last updated Jul 24, 2026. Interested? Apply on the company site.
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