ASIC Verification Engineer
NVIDIA· Engineer, Verification
Santa Clara, CA$116k - $189.8kfull-timePosted 2mo ago
About the role
NVIDIA’s Clocks team seeks an experienced ASIC Design Verification engineer to validate clocking and reset logic across SOC and GPU products, delivering bug-free designs through end-to-end verification, automation, and scalable methodologies.
Responsibilities
- Own validation of Clocking structures in Tegra and GPU products from start to finish, including test plan development, automation, validation flows development, coverage metrics, test execution, bug identification/fix and productization.
- Tackle sophisticated problems and develop a scalable solution that works across platform.
- Hands on industry-standard tools and state of the art verification methodologies, including SystemVerilog, UVM, C++, Perl, Python and NVIDIA custom compilers and tools.
- Partnering closely with clocks architecture and design team to validate clocks design.
- Coordinate with internal and external teams across time zones.
Qualifications
- BS or MS in EE/ECE or equivalent experience
- 3+ years of proven design verification experience
- Good understanding of Logic Design and Architecture
- Expertise in SV constraint random verification, UVM, Formal Verification, Coverage metrics, profiling tools, X prop, etc
- Exposure on block level and system-level verification
- Strong coding skills in System Verilog, scripting languages (Perl/python), and C++
- Ability to collaborate and work with multiple groups
- Prior experience in implementing Test plans for pre-silicon platforms
Skills
Required:SystemVerilogUVMC++Perl/Python
Benefits
- equity
- benefits (see company benefits link)
Last updated Oct 9, 2026. Interested? Apply on the company site.
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