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ASIC Design and STA Engineer

NVIDIA· Engineer, ASIC
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Hybrid (Bengaluru, India), Hybrid (Hyderabad, India)full-timePosted 2mo ago

About the role

NVIDIA is seeking an ASIC STA Engineer to join the Networking Silicon engineering team, focusing on high-speed communication devices, with emphasis on timing convergence, floor planning, and signoff across chip and chiplet levels.

Responsibilities

  • Be in charge of full chip and/or chiplet level STA convergence from early stages to signoff.
  • Take part in top level floor plan and clock planning.
  • Optimize, together with CAD signoff flows and methodologies.
  • Digital Partitions' and analog IPs' timing integration, giving feedback to PD/RTL and driving convergence.
  • Work closely with logic design and DFT engineers to define and implement constraints for the various work modes, including their optimization for runtime and efficiency.

Qualifications

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering.
  • 3+ years of experience in physical design and STA
  • Proven experience in RTL2GDS and STA design and convergence
  • Familiarity with physical design EDA tools (such as Synopsys, Cadence, etc.)
  • Hands on STA experience from early stages to signoff using Synopsis Primetime. Deep knowledge in timing concepts required.
  • Great teammate.

Skills

Required:STA (Static Timing Analysis)RTL2GDSphysical designfloor planning
Last updated Jul 31, 2026. Interested? Apply on the company site.

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