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ASIC TOP Floorplan Design Engineer

NVIDIA· Engineer, ASIC
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Shanghainot specifiedPosted 2mo ago

About the role

ASIC Floorplan Engineer to design and optimize floorplans for SoCs/GPUs, drive area reviews, solve timing/routing issues, and build tools using AI to optimize chip area and speed.

Responsibilities

  • Develop, craft and optimize floorplans during early chip development with architects and leads.
  • Drive the area review process and collaborate with the ASIC design team to identify area, interconnect and floorplan improvement opportunities.
  • Solve timing and routing congestion issues with physical and ASIC design teams by influencing early design and physical implementation decisions.
  • Build tools and improve existing infrastructure using AI extensively to optimize chip area and speed of execution.

Qualifications

  • Master’s degree in electrical engineering, Computer Science, or Computer Engineering and 1+ year equivalent work/learning experience.
  • Experience in Verilog, System Verilog or similar HVL.
  • Experience with CAD and physical design methodologies (flow and tool development), chip floorplan, power/clock distribution, packaging, P&R and timing closure.
  • Strong communication and interpersonal skills and ability & desire to work as a great teammate.
  • Python, Perl and C/C++ programming language experience.
  • Experience using AI coding assistants like Cursor or Github Copilot or Windchill.

Skills

Required:Verilog/SystemVerilogCAD and physical design methodologiesFloorplanningPythonPerlC/C++AI toolingCommunication
Last updated Aug 7, 2026. Interested? Apply on the company site.

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