Physical Design Engineer, Synthesis and Implementation
NVIDIA· Engineer, Phys Design
US, MA, Westford$116k - $189.8kFull-timePosted 2mo ago
About the role
NVIDIA seeks a Physical Design Engineer with expertise in Synthesis to join the Networking Silicon engineering team, focusing on RTL-to-gate synthesis, QoR optimization, and full physical design flow from floorplanning to timing closure for high-speed communication devices.
Responsibilities
- Own RTL-to-gate synthesis and QoR convergence for complex digital blocks and hierarchical partitions
- Optimize synthesis strategies, constraints, and flows to meet performance, power, and area targets
- Analyze design bottlenecks and QoR regressions, collaborating with RTL, timing, architecture, and physical design teams to resolve them
- Support physical implementation from floorplanning and power planning through routing and timing closure
- Automate design setup, execution, reporting, and issue triage while improving project-wide methodologies and best known methods
Qualifications
- BSEE, MSEE, or equivalent experience
- 2+ years of experience in synthesis and physical implementation on advanced process nodes
- Strong proficiency with Synopsys Fusion Compiler, Cadence Genus, or comparable synthesis tools
- Hands-on experience with synthesis constraints, timing analysis, QoR optimization, and the full place-and-route flow
- Strong analytical and debugging skills across RTL, synthesis, timing, and physical implementation
- Proficiency in Python, Perl, Tcl, and Make
- Strong communication and multi-functional collaboration skills
Skills
Required:RTL-to-gate synthesisQoR optimizationSynthesis toolsPlace-and-routeDesign analysisProgramming/scripting
Benefits
- equity
- benefits (as per company offerings)
Last updated Oct 9, 2026. Interested? Apply on the company site.
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