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Senior Mask Design Engineer – Hardware

NVIDIA· Engineer, Sys Design
Apply on company site
Santa Clara, CA, Remote$136k - $212.8kFull-timePosted 2mo ago

About the role

Senior Mask Design Engineer focused on designing and developing detailed silicon interposer layouts for NVIDIA products, collaborating with PTL and multiple design teams to meet schedules and optimize packaging, layout, and verification goals.

Responsibilities

  • Collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solutions for product packages on tight schedules
  • Perform physical layout for silicon interposer using Cadence tools
  • Conduct design feasibility studies to evaluate package design goals for size, cost, and system performance
  • Study layout floorplan and perform custom layout and verification against design rules and netlists
  • Propose layout design trade-offs to the PTL for resolution and implementation

Qualifications

  • B.S. Electrical Engineering or equivalent experience
  • Minimum of 5+ years proven experience in Mask and Layout Design
  • Deep understanding of layout concepts in submicron CMOS technologies
  • Proficient with Cadence layout tools - Virtuoso
  • Knowledge of Integrity auto-routing is a plus
  • Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
  • Proficient in scripting languages like Perl, Python, Skill, etc.
  • Knowledge of DRC and LVS checking flows, ability to customize decks
  • Knowledge of APD package layout tool is a plus
  • Good understanding of packaging technology is useful
  • Strong teamwork, interpersonal skills, passion and positive energy

Skills

Required:Mask designCadence VirtuosoLayout verification toolsScripting

Benefits

  • Equity
  • Benefits (as per company policy)
Last updated Oct 23, 2026. Interested? Apply on the company site.

About NVIDIA

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NVIDIA invents the GPU and drives advances in AI, HPC, gaming, creative design, autonomous vehicles, and robotics.

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