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Senior System Integration Engineer, Memory

NVIDIA· Engineer, ASIC
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Hybrid (Santa Clara, CA), Remote$196k - $310.5kFull-timePosted 2mo ago

About the role

Senior Memory Systems Engineer responsible for HBM and LPDDR integration in sophisticated SoCs, overseeing full-stack memory integration from silicon bringup to production, with emphasis on system-level memory challenges, validation, and cross-domain collaboration.

Responsibilities

  • HBM & LPDDR System Integration and Bringup: Drive HBM and LPDDR system integration, bringup, characterization, and debug for next-generation SoCs — taking memory subsystems through the full arc from first silicon to production-ready at scale.
  • Full-Stack Memory Closure: Own memory performance, power management, thermal, and reliability closure across silicon, package, board, and firmware — translating characterization results into signed-off operating points and release criteria that the full program depends on.
  • Post-Silicon Margining, VF Shmoo & Correlation: Lead post-silicon margining, VF shmoo, eye, and correlation work across voltage, temperature, and frequency — building the characterization foundation that underpins every product decision downstream.
  • Memory Debug: Training, Calibration, SI/PI & Stability: Debug and resolve memory training, calibration, SI/PI, and system-level stability issues — the class of problems that sit at the intersection of electrical, physical, and software behavior and demand deep cross-domain expertise to resolve at scale.
  • Validation & Characterization Planning: Define validation, characterization, and issue-tracking plans across chip programs — building the framework that ensures the right tests exist, the right data gets collected, and issues are tracked with enough fidelity to close.

Qualifications

  • BS or MS in EE/CE — or equivalent experience.
  • 12+ years in HBM, LPDDR, or high-speed memory systems, with hands-on depth in silicon bringup, characterization, and debug at scale. PHY controller development experience is a significant plus and will set you apart.
  • Deep command of SI/PI, timing, margining, and memory training behavior — and the multi-functional fluency to work across design, package, firmware, validation, and product teams without losing the thread.
  • HBM PHY and controller architecture familiarity is useful context, but the role requires system-level instinct to foresee memory-related product problems and resolve them proactively.

Skills

Required:HBM & LPDDR system integrationSI/PI, timing, margining, memory trainingCross-domain collaboration
Nice to have:HCM, HBM PHY/controller architecture

Benefits

  • equity
  • benefits (as per company benefits page)
Last updated Sep 25, 2026. Interested? Apply on the company site.

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