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ASIC Design Engineer, Clocks

NVIDIA· Engineer, ASIC
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Hybrid (Shanghai)Full-timePosted 2mo ago

About the role

Senior ASIC Design Engineer role in NVIDIA's GPU clocks group focusing on designing, validating, and integrating high-frequency, low-power clocking RTL for GPUs, collaborating with multiple teams across frontend, backend, SOC verification, timing, and DFT.

Responsibilities

  • Collaborate with architects, ASIC designers, and verification engineers to design high-frequency and low-power clocks.
  • Engage with multiple teams to ensure GPU clocks satisfy architectural constraints.
  • Run and enhance in-house flow to guarantee quality of clocks RTL and netlist; drive issues to closure.
  • Deliver clock information to SOC verification, timing, and DFT teams.
  • Use Perl/Python to improve productivity of involved teams.
  • Collaborate with software and silicon solution teams to debug GPU clock silicon bugs in new products.

Qualifications

  • BS in Electrical Engineering (MS preferred) or equivalent experience
  • 2+ years of relevant work experience
  • Validated experience in RTL design (Verilog), verification and logic synthesis
  • Strong coding skills in Perl or Python (or other industry-standard scripting languages)
  • Fluent English (written and spoken) with excellent communication skills
  • Good teamwork and collaboration skills

Skills

Required:RTL designVerificationLogic synthesisScripting
Last updated Aug 7, 2026. Interested? Apply on the company site.

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