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CAD Developer, IR, Timing and Physical Design Optimization

NVIDIA· Engineer, ASIC
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Shanghaifull-timePosted 2mo ago

About the role

ASIC-PD team hires both junior and senior engineers for physical design from RTL to GSDII, including design quality check, synthesis, formal check, partitioning, constraints, timing analysis/fixing/signoff, and related flows. Collaborate with ASIC/P&R/DFT/SI/ARCH teams to drive physical-friendly design on the most advanced process/technology.

Responsibilities

  • Invent and optimize new methods for increasing chip frequency while minimizing power consumption across a suite of internal optimization tools.
  • Improve algorithms (in C++) for IR drop optimization, simulation
  • Own the whole process from discovery of optimization opportunities to developing solutions and deploying them inside design teams.

Qualifications

  • BS, MS, PhD in Electrical Engineering or Computer Science or equivalent experience
  • Minimum 2+ years of relevant experience in CAD software and VLSI hardware design
  • Strength in both CAD software and VLSI design
  • Understanding of VLSI IR drop optimization or simulation and related concepts, including constraints, corner, CCSP, FSDB etc.
  • Demonstrated ability in software development using C++
  • Strong communication and interpersonal skills

Skills

Required:C++IR drop optimizationCAD/EDA tools
Last updated Aug 7, 2026. Interested? Apply on the company site.

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