Senior Memory Post Silicon Qualification Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA$168k - $264.5kFull-timePosted 2mo ago
About the role
Senior-level role in NVIDIA's Silicon Co-Design Group responsible for high-speed memory bring-up, characterization, and qualification across GPU, CPU, and SoC programs, with a focus on root-cause analysis, AI-enabled data workflows, and cross-team collaboration.
Responsibilities
- Bring up high-speed memory interfaces (GDDR, LPDDR, HBM) on complex GPU, CPU and SoC silicon — from first power-on through full PVT characterization and productization.
- Own functional validation, IO tuning, timing margin analysis, and multi-vendor DRAM qualification across the memory controller, PHY, and DRAM device — for the full matrix of capacities, speeds, and configurations we ship.
- Lead root-cause closure on the hardest multi-team memory failures — spanning silicon, controller, PHY, package, board SI/PI, firmware, and workload — with reusable workarounds and productized fixes.
- Design and deploy AI-enabled workflows for margin data analysis, shmoo bucketing, failure signature detection, and workload-vs-margin correlation — with guardrails for trustworthy outputs in qualification decisions.
- Partner with pre-Si architecture, design, and DV teams to translate new memory features into post-Si validation plans, and feed post-Si learnings back into pre-Si methodology.
- Work across globally distributed teams — silicon design, PHY, PCB, firmware, software, DRAM vendors, and manufacturing partners — including Taiwan and other major hubs.
Qualifications
- B.Tech or M.Tech in Electrical, Electronics, or Computer Engineering (or equivalent experience)
- 10+ years in the semiconductor industry with at least 3 years directly on memory interface bring-up, characterization, and qualification on shipped silicon
- Deep protocol and physical-layer understanding of GDDR, LPDDR, or HBM — training, calibration, IO tuning, timing margin, and vendor-to-vendor behavior differences
- At least one concrete example of taking an ambiguous memory failure to root-cause closure with a productized fix
- Strong hands-on lab fundamentals — oscilloscope, DMM, thermal chambers, protocol analyzers
- Working knowledge of PCB stack-up, board layout, power planes, and SI/PI guidelines related to memory issues
- Demonstrated AI-driven workflow for memory characterization, margin analysis, or failure triage with measurable impact on debug velocity, coverage, or escape rate
Skills
Required:High-speed memory bring-up and qualificationRoot-cause analysis of memory failuresAI-enabled data workflows for memory characterization
Benefits
- Equity and benefits (details available in benefits page)
- Competitive benefits
- Flexible time off
- Continuous learning
Last updated Oct 2, 2026. Interested? Apply on the company site.
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