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SOC Clocks RTL Design Engineer

NVIDIA· Engineer, ASIC
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Israel (Tel Aviv / Beersheva / Yokneam)full-timePosted 2mo ago

About the role

RTL design role focused on owning SOC clocking logic for NVIDIA’s next-generation networking chips, including clock generation, distribution, and control logic (PLL, reference clocks, muxing, dividers, glitchless switching, gating, reset synchronization, CDC). Collaboration with micro-architecture, DV, backend, and software/DFT teams to deliver synthesizable RTL from spec through tape-out and silicon.

Responsibilities

  • Owning the SOC clocking logic end to end: writing synthesizable Verilog/SystemVerilog RTL for clock generation, distribution, muxing, division, glitchless switching, gating, and reset synchronization, from micro-architecture specification through tape-out
  • Defining and implementing the SOC clock and reset architecture with the micro-architecture team — translating requirements into a coherent, verifiable design
  • Owning clock domain crossing infrastructure and CDC closure across the SOC
  • Reviewing specifications with the micro-architecture team and providing feedback on implementation cost, timing, area, and power
  • collaborating with Physical Design on clock tree implementation, constraints, partitioning, floorplanning, timing feedback, synthesis, congestion, and timing convergence
  • Supporting Software and firmware teams on clock programming sequences, DVFS, and low-power/clock-shutdown flows
  • Driving design quality: lint, CDC/RDC, formal checks, synthesis QoR, connectivity and structural checks
  • Supporting SOC-level chip build and assembly, and developing automation flows for RTL integration and design quality checks
  • Supporting emulation, firmware, and post-silicon bring-up customers of your design

Qualifications

  • B.Sc./M.Sc. in Electrical Engineering or Computer Engineering
  • 3+ years of relevant experience in RTL/logic design
  • Solid hands-on RTL design skills in Verilog/SystemVerilog, with understanding of synthesis, timing, and how RTL choices affect physical implementation
  • Experience taking a design from micro-architecture specification through verification and physical implementation
  • Solid understanding of clocking and reset concepts: clock gating, clock muxing and dividers, glitchless clock switching, reset synchronization, and clock domain crossing
  • Familiarity with design quality tooling (lint, CDC/RDC, formal, synthesis)
  • Great teammate with strong communication skills across micro-architecture, DV, and backend teams

Skills

Required:Verilog/SystemVerilogClocking and reset conceptsClock domain crossing (CDC)Collaboration with back-end/physical design

Benefits

  • Equal opportunity employer
  • Diversity and inclusion
  • Competitive compensation and benefits (as per company policy)
Last updated Aug 7, 2026. Interested? Apply on the company site.

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