HSIO Validation Lead – Silicon Co-Design
NVIDIA· Engineer, ASIC
Santa Clara, CA$168k - $264.5kFull-timePosted 2mo ago
About the role
Role leading end-to-end HSIO validation and debug for PCIe, NVLink, C2C and other high-speed interfaces across NVIDIA GPUs, CPUs, and SoCs from post-silicon bring-up to production readiness, owning strategy, methodology, and cross-stack collaboration to ensure robust interfaces.
Responsibilities
- Own post-silicon bring-up, characterization, validation, and debug of PCIe, NVLink, C2C, and other HSIO interfaces across NVIDIA GPUs, CPUs, and SoCs from first power-on through production readiness.
- Close the hardest failures. Drive root cause across protocol behavior, signal integrity, firmware and driver interactions, platform topology, and silicon marginalities and own every fix through to confirmation.
- Define validation strategy. Set test coverage, debug priorities, margining methodology, and stress criteria for each program.
- Own and build AI agents that operate under your direction. These include automated debug triage, intelligent data pipelines, and analysis flows.
- Ensure robust interoperability across the full ecosystem: retimers, switches, accelerators, CPUs, GPUs, and sophisticated multi-device system topologies.
- Sit at the decision table. Your analysis drives alignment across architecture, logic design, circuit design, firmware, drivers, ATE, DGX, and product teams.
- Translate what you learn on real silicon into methodology and coverage improvements that make future products harder to escape.
Qualifications
- BS or MS in Electrical Engineering, Computer Engineering, or Systems Engineering, or equivalent experience in the lab.
- 8+ years in silicon validation, HSIO bring-up, or high-speed interface debug on real hardware.
- Deep protocol expertise in PCIe, NVLink, CXL, C2C, Ethernet, USB, or similar high-speed interface technologies.
- Strong signal integrity fundamentals: SERDES behavior, link training, equalization, clocking, reset, power management, and high-speed board and system interactions.
- Hands-on lab depth: oscilloscopes, BERTs, protocol analyzers, logic analyzers, exercisers, and silicon debug tools.
- The ability to debug across the full stack, hardware, firmware, drivers, and platform design, without losing the thread.
- Enough statistical proficiency to recognize moments a marginal distribution is telling you something and enough intuition to know where to look next!
Skills
Required:Post-silicon bring-up and validationProtocol and signal integrityDebug across full stack
Benefits
- equity
- benefits
Last updated Sep 25, 2026. Interested? Apply on the company site.
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