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Physical Design STA Engineer

NVIDIA· Engineer, ASIC
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Israel, Yokneam, Israel, Tel AvivFull-timePosted 2mo ago

About the role

NVIDIA is seeking a Physical Design CAD Engineer to join the Networking Silicon engineering team, focusing on physical design, STA, power integrity, and related flows for networking chips and SOCs, with opportunities to contribute to timing analysis, power/noise, IR-drop, EM, and backend verification.

Responsibilities

  • Develop physical design, STA, Logic eq, Power Integrity flows and methodologies for implementation of networking chips and SOCs.
  • Work closely with block owners and full Chip STA engineers to assure high quality and timely convergence.
  • Propose unique and creative solutions to advanced physical design problems for NVIDIA chips.
  • Develop and contribute to flow and tool methodologies for timing analysis and closure, power and noise analysis, IR-drop, EM, and backend verification across multiple projects.

Qualifications

  • B.SC./ M.SC. in Electrical Engineering/Computer Engineering (or equivalent experience).
  • 2+ years of full-time relevant experience in Physical Design, STA and timing closure methodologies.
  • Proven experience and strong knowledge in Physical Design, STA and timing closure methodologies.
  • Familiarity with PrimeTime (STA) and PrimePower (Power Estimation).
  • Self-motivation, attention to detail, and good written, verbal, and presentation skills.
  • Strong sense of ownership, self-learning skills, and ability to work independently and with internal/global teams.

Skills

Required:Physical DesignStatic Timing Analysis (STA)Timing closure methodologiesPrimeTimePrimePower
Nice to have:Power IntegrityRedHawkFormalityTcl/Perl/Python
Last updated Aug 14, 2026. Interested? Apply on the company site.

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