Senior ASIC Power Management Micro Architect, Chip Design
NVIDIA· Engineer, ASIC
Israel, Yokneam, Israel, Tel Avivfull-timePosted 2mo ago
About the role
Senior ASIC Design Engineer focused on Power Management IP, leading front-end micro-architecture from definition to post-silicon enablement within NVIDIA’s Chip Design team.
Responsibilities
- Owning the front-end micro-architecture and design of Power Management IP ASIC blocks, from the IP definition phase through the full design cycle and into post-silicon bring-up and enablement.
- Serving as a key player in the development and enablement of new power management technologies across NVIDIA's product lines.
- Delivering high-quality, synthesizable RTL as part of the IP Chip Design team.
- Partnering closely with architecture, verification, physical design, and validation teams to drive successful tape-out and silicon bring-up.
- Leading post-silicon debug, characterization, and enablement activities to bring your blocks from concept to working silicon.
Qualifications
- BSc or MSc in Electrical Engineering, Computer Engineering, or a related field (or equivalent experience).
- 12+ years of hands-on RTL design experience.
- Proven experience bringing a block from the development phase all the way through to post-silicon bring-up and enablement.
- Strong background in front-end ASIC micro-architecture and design.
- Solid command of the full IP/ASIC design flow, from definition through post-silicon.
- A collaborative mindset and the drive to be a key contributor within a world-class design team.
Skills
Required:Front-end ASIC micro-architectureRTL designIP/ASIC design flowPost-silicon bring-upCross-functional collaboration
Last updated Aug 21, 2026. Interested? Apply on the company site.
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