Senior STA Signoff Methodology Engineer
NVIDIA· Engineer, ASIC
Santa Clara, CA, Austin, TX$168k - $310.5kfull-timePosted 2mo ago
About the role
Senior STA Signoff Methodology Engineer to drive sign-off strategies for GPUs, CPUs, LPUs and SoCs; optimize performance, yield, and reliability through modeling, analysis, and automation across NVIDIA product lines.
Responsibilities
- Run large-scale SPICE simulations and STA experiments to model the impact of advanced technologies on chip timing.
- Develop STA and PNR flows and recommendations addressing aging, self-heating, thermal effects, IR drop, electro migration, and other advanced-node physical effects.
- Collaborate with technology leads, physical-design engineers, and timing engineers to define and deploy sophisticated timing-signoff strategies for extraordinary silicon performance.
- Develop tools and methodologies that improve design performance, predictability, and silicon reliability beyond the capabilities of standard EDA tools.
- Work across STA, constraints, and timing and power optimization.
- Perform extensive data analysis using Python, JMP, or similar tools to improve STA-to-silicon correlation.
Qualifications
- MS in Electrical or Computer Engineering, or equivalent experience, with 8 years of experience in ASIC design and timing.
- Solid understanding of RC extraction, device physics, STA methodologies, and EDA-tool limitations.
- Proven foundation in the mathematics and physics underlying electrical design.
- Experience with low-power techniques, including multi-Vt design, clock gating, power gating, activity-based power analysis, DVFS, and CDC.
- Understanding of signal and power integrity, crosstalk, electromigration, noise, OCV, timing margins, clock jitter, and IR drop.
- Understanding of standard-cell, memory, and I/O IP modeling and their use in ASIC flows.
- Hands-on experience with advanced FinFET and emerging CMOS technologies at 5 nm, 3 nm, 2 nm, and beyond.
- Familiarity with industry-standard ASIC tools such as PrimeTime, ICC2, RedHawk, and Tempus.
- Strong communication skills and a collaborative working style.
Skills
Required:SPICE simulationsSTA methodologiesRC extractionLow-power techniquesSignal/power integrityIP modelingFinFET/CMOS techEDA toolsData analysis with Python/JMP
Nice to have:Programming languages
Benefits
- equity and benefits (per company offerings)
Last updated Aug 21, 2026. Interested? Apply on the company site.
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