Senior ASIC Verification Engineer - HSIO
NVIDIA· Engineer, Verification
Hybrid (Westford, MA), Hybrid (Austin, TX)$136k - $218.5kfull-timePosted 2mo ago
About the role
Senior Design Verification Engineer to verify High Speed I/O controller designs (e.g., Ethernet, NVLink) for ASIC/IP/sub-systems using advanced DV methodologies (UVM); emphasizes reusable verification components, test planning, and cross-team collaboration.
Responsibilities
- Be responsible for the verification of ASIC design, architecture, golden models and micro-architecture of High Speed I/O controllers, like Ethernet and NVLink, at IP/sub-system levels using advanced DV methodologies such as UVM.
- Building reusable bus functional models, monitors, checkers and scoreboards following coverage driven verification methodology.
- Understanding the design specification and implementation, defining the verification scope, developing test plans, tests, and the verification infrastructure used to verify the correctness of the design.
- Collaborating with architects, designers, and pre and post silicon verification teams to accomplish your tasks.
Qualifications
- Bachelors or Masters Degree (or equivalent experience) with 5+ years of relevant experience
- Experience at Unit/Sub-system/SOC level and expertise in SystemVerilog, UVM
- Expertise in comprehensive verification of IP or interconnect protocols (e.g. Ethernet, USB, SATA)
- Experience in verification using random stimulus along with functional coverage and assertion-based verification methodologies (UVM) and exposure to industry standard verification tools for simulation
- Excellent debugging, analytical, and problem solving skills
- Great communication and collaboration skills to interact within the team and across functional teams
Skills
Required:SystemVerilogUVMIP/interconnect protocol verificationrandom stimulus & coverage-driven verificationdebugging and problem solving
Benefits
- equity
- benefits (see NVIDIA benefits)
Last updated Aug 21, 2026. Interested? Apply on the company site.
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