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Senior Signal and Power Integrity Engineer

NVIDIA· Engineer, ASIC Signal Integrity
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Santa Clara, CA$136k - $218.5kfull-timePosted 2mo ago

About the role

Senior SI/PI engineer responsible for lead board/system SI design, PDN optimization, and collaboration with design teams to ensure high-speed interface performance across PCIe, memory interfaces, HDMI, USB, and other interfaces.

Responsibilities

  • Lead board/system SI design activities, PCB stack up design, material selection, design guide implementation, layout review, and post-layout analysis.
  • System-level signal integrity simulation of PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, USB and other interfaces.
  • Analyze and optimize Power delivery network (PDN) on PCBs.
  • Work closely with Package and PCB Design teams crafting solutions for system SI/PI performance.
  • Work with Application Engineering supporting customer board designs.
  • TDR & VNA measurement for PKG/PCB material characterization and model correlation

Qualifications

  • BS/MS in Electrical Engineering (or equivalent experience) with minimum 4 years of experience as a SI/PI engineer
  • Good understanding of electromagnetics, channel components and transmission line theory
  • Experience with design and implementation of one or more high speed electrical interfaces, such as PCIE, LPDDR/DDR/GDDR, MIPI, HDMI, USB etc.
  • Hands on experience with HFSS, Sigrity, Hspice or similar industry standard simulation tools
  • Experienced with Cadence Allegro PCB designer and Constraints Manager and or other PCB stack up designer tools.
  • Understanding of impacts of high-volume PCB manufacturing on channel signal integrity

Skills

Required:Signal integrity (SI)Power integrity (PI)High-speed interface designElectromagnetics / transmission line theory

Benefits

  • Equity
  • Benefits package
Last updated Aug 21, 2026. Interested? Apply on the company site.

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