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Senior DFT Design/Micro architect Engineer, Google Cloud

Google· Google Cloud - AI/Infrastructure (DFT specialization)
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BengaluruFull-timePosted 2mo ago

About the role

Senior DFT Design/Micro architect Engineer role focusing on design-for-testing (DFT) for TPU hardware within Google Cloud’s AI/Infrastructure initiatives. Involves shaping DFT strategy, validating die-level DFT, and delivering test patterns for production and post-silicon support.

Responsibilities

  • Develop DFT strategy and architecture (e.g., hierarchical DFT, DFT for High speed I/O, Analog DFT).
  • Develop and drive die level DFT validation strategy and complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
  • Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
  • Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
  • Generate and deliver the production and debug patterns to Post Silicon engineering team and run diagnosis for post silicon supports.

Qualifications

  • Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience.
  • 8 years of experience in the implementation and validation of DFT technologies.
  • Experience with multiple projects in DFT design and verification, DFT specification, definition, architecture, and insertion.
  • Experience with DFT techniques and tools, ASIC DFT synthesis, simulation, and verification flow.
  • Experience in leading DFT activities throughout an ASIC development flow.

Skills

Required:DFT strategy and architectureDFT validationDFT IP insertionDigital/ASIC design and verification
Last updated Oct 23, 2026. Interested? Apply on the company site.

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