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ASIC Physical Design Intern - 2027

NVIDIA· Intern
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ShanghaiinternPosted 1mo ago

About the role

ASIC-PD intern role at NVIDIA focusing on RTL-to-tapeout tasks including synthesis, verification, timing closure, and flow automation across chip integration, floorplanning, and backend timing, with opportunities to contribute to full-chip timing closure and methodology improvements.

Responsibilities

  • Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan
  • Synthesis, RTL/netlist quality check, formal verification, function eco creation
  • Constraints creation and validation, timing budget, analyze/resolve function timing issues with ASIC team to achieve timing closure (io, test, clock, async, etc.)
  • Work with PR engineers for chip implementation to achieve full chip timing closure
  • Develop and improve timing closure flow from frontend (pre-layout) to backend (post-layout), and flow automation for above areas
  • Methodology in any of the above areas.

Qualifications

  • Currently pursuing a Master's or PhD degree within a relevant or related field
  • Strong knowledge in IC design
  • Passionate about technology research and IC backend
  • Self-driven, good learning ability, good teamwork
  • Excellent communication skill, proficient in English reading and writing

Skills

Required:IC design knowledgeRTL-to-netlist workflowTiming closureConstraints creation
Nice to have:Formal verificationPythonTCL
Last updated Aug 28, 2026. Interested? Apply on the company site.

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