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ASIC Physical Design Engineer (RDSS Intern)

NVIDIA· Intern
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Hsinchu, TaiwaninternPosted 1mo ago

About the role

NVIDIA RDSS intern role in ASIC physical design, focusing on RTL-to-tapeout tasks, timing closure, constraints, verification, and flow development for advanced process nodes.

Responsibilities

  • Chip integration and netlist generation
  • Synthesis
  • RTL/netlist quality check
  • Formal Verification
  • Constraints creation and validation, timing budget
  • Work with ASIC team to analyze/resolve special timing issues
  • Cross-Team collaboration to implement chip partitioning and floorplan
  • Work with PR engineers to achieve timing closure for both partition and full chip level
  • Achieve special mode timing closure, such as IO, test, clock, async etc.
  • Function eco creation
  • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout)
  • Flow automation development for above areas
  • Methodology in any of above areas.

Qualifications

  • MS in EE or Microelectronics
  • Project experience in IC design implementation
  • Courses taken in circuit design, digital design
  • Hand-on experience in EDA software from Synopsys (DC/PT/Formality), Cadence (RC compiler/LEC) is helpful
  • Proficient user of Python or TCL is helpful
  • Proficient in English reading and writing

Skills

Required:VLSI/ASIC design
Nice to have:Scripting

Benefits

  • Competitive salaries
  • Generous benefits package
Last updated Aug 28, 2026. Interested? Apply on the company site.

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