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ASIC Physical Design Intern - 2027

NVIDIA· Intern
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Taiwan, HsinchuinternPosted 1mo ago

About the role

ASIC-PD intern role at NVIDIA focusing on physical design tasks from RTL to tape-out, including synthesis, formal verification, constraints, timing closure, and flow automation in a high-frequency, low-power environment for ASIC back-end development.

Responsibilities

  • Chip integration and netlist generation, cross-team collaboration to implement chip partitioning and floorplan
  • Synthesis, RTL/netlist quality check, formal verification, function eco creation
  • Constraints creation and validation, timing budget, analyze/resolve function timing issues, achieve all special timing closure (io, test, clock, async)
  • Work with PR engineers for chip implementation to achieve full chip timing closure
  • Develop and improve entire timing closure flow from frontend (pre-layout) to backend (post-layout), flow automation development for above areas
  • Methodology in any of the above areas.

Qualifications

  • Currently pursuing a Master's or PhD degree within a relevant or related field
  • Strong knowledge in IC design
  • Passionate about technology research and IC backend
  • Self-driven, good learning ability, good teamwork
  • Excellent communication skill, proficient in English reading and writing

Skills

Required:IC designScripting languages (Python or TCL)Communication
Nice to have:flow automationEDA tools (Synopsys DC/PT/Formality, Cadence RC compiler/LEC)
Last updated Aug 28, 2026. Interested? Apply on the company site.

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