Senior Mask Design Engineer – Hardware
NVIDIA· Engineer, Sys Design
Taiwan, Hsinchufull-timePosted 1mo ago
About the role
Senior Mask Design Engineer for silicon interposer layout, collaborating with PTL and design teams to plan schedules, resolve costs, manufacturing and electrical design issues, and performing physical layout using Cadence tools.
Responsibilities
- Collaborate cross functionally with package technical lead (PTL) and I/O signal integrity and technology engineers to deliver solution for product packages in tight schedule.
- Perform physical layout for silicon interposer using Cadence tools.
- Conduct design feasibility studies to evaluate the package design goals for size, cost, and system performance.
- Take part in studying layout floorplan and perform custom layout and verification against design rules and netlists.
- Propose layout design trade-offs to the PTL for resolution and implementation.
Qualifications
- Hold a B.S. Electrical Engineering or equivalent experience
- Minimum of 5+ years proven experience in Mask and Layout Design
- Deep understanding of layout concepts in submicron CMOS technologies
- Authority with Cadence layout tools - particularly Virtuoso
- Knowledge of Integrity auto-routing is a plus
- Experience running and debugging with verification tools such as Calibre, ICV, Thunder, etc.
- Proficient in scripting languages like Perl, Python, Skill, etc.
- Knowledge of DRC and LVS checking flows, ability to customize decks
- Knowledge of APD package layout tool is a plus
Skills
Required:Mask and Layout DesignCadence VirtuosoDRC/LVSScripting (Perl, Python, Skill)Verification Tools
Benefits
- Competitive salaries
- Generous benefits package
Last updated Aug 28, 2026. Interested? Apply on the company site.
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