Physical Design Engineer, SoC Static Timing Analysis
Tel Aviv, Israel; Haifa, IsraelFull-timePosted 1mo ago
About the role
Mid-level role focused on shaping AI/ML hardware acceleration by driving sign-off timing convergence and STA methodology for high-performance SoC designs, with emphasis on TPU architecture integration and collaboration across block owners and logic designers.
Responsibilities
- Drive the sign-off timing convergence for high-performance designs.
- Set up the timing constraints, define the overall static timing analysis (STA) methodology, establish the STA infrastructure and sign-off convergence flows, and work closely with block owners for sign-off timing convergence.
- Work with logic designers to drive architectural feasibility studies, develop timing, and explore RTL/design trade-offs for physical design closure.
Qualifications
- Bachelor's degree in Electrical Engineering, a related technical field, or equivalent practical experience.
- 8 years of Physical Design experience including 5 years of experience with Static Timing Analysis (STA), including sign-off corner definitions, process margining, interface timing constraints, timing convergence, and setting frequency goals with technology scaling.
- Experience in constraints development for subsystems or full System-on-Chip (SoC) architectures.
Skills
Required:Static Timing Analysis (STA)Constraints development
Nice to have:Scripting languages (Tcl, Python, Perl)
Last updated Oct 23, 2026. Interested? Apply on the company site.
More open roles at Google
- Staff Network Security Engineer, Google Enterprise Network2d agoHybrid (Austin, TX; Sunnyvale, CA)
- Group Product Manager, Google Lens AI Shopping2d agoMountain View, CA, USA · Product Management
- UX Program Manager2d agoHybrid (New York, NY; San Bruno, CA) · UX Programs & Operations
- Senior Staff Software Engineer, Android Automotive OS2d agoHybrid (Kraków, Poland; Munich, Germany)
- 2d ago