Member of Technical Staff, GPU Kernels
About the role
Role focused on GPU kernel engineering and optimization to push the performance envelope across NVIDIA, AMD, TPU, and Trainium, with emphasis on hand-written kernels, profiling, and integration with a custom compiler stack.
Responsibilities
- Write and hand-optimize kernels for real workloads to push performance ceilings before the search space is explored by the compiler.
- Profile at microarchitectural level (SM and CU utilization, warp stalls, memory bank conflicts, register pressure, instruction throughput, occupancy tradeoffs).
- Debug down to clock behavior, thermal throttling, and driver paths where documentation may be missing or inaccurate.
- Turn hard-won kernel knowledge into machine-searchable structures for the compiler to explore.
- Reason about SASS and cubins, working below PTX at the ISA level to emit schedules PTX cannot express.
- Build performance models, microbenchmarks, and tooling to predict kernel behavior.
- Collaborate with the formal correctness team to ensure aggressive kernels ship with formal proofs.
Qualifications
- Track record of hand-writing kernels that match or beat vendor libraries.
- Comfort reading PTX, SASS, GCN/CDNA ISA or equivalent machine-level assembly.
- Fluent with low-level profiling tools (Nsight Compute, Nsight Systems, rocprof, omniperf or equivalents).
- Solid systems programming skills in C++ and CUDA or ROCm/HIP with understanding of how high-level ML ops map to hardware.
Skills
Benefits
- Equity
- Benefits (unspecified in detail in description)

About SF Tensor
Infrastructure for AI labs to focus on research.
AI researchers should be pushing the boundaries of what's possible with new architectures and training methods. Instead, they waste weeks configuring cloud infrastructure, debugging distributed systems, and optimizing their GPU code. We know because we lived it: While training our own models across thousands of GPUs earlier this year, we spent more time fighting our infrastructure than doing actual research. That why we're building two things. First, Elastic Cloud: a managed platform that automatically finds the cheapest GPUs across all providers, handles spot instance preemption, and cuts compute costs by up to 80%. Second, automatic kernel optimization that makes training code run faster by modeling hardware topology, often beating hand-tuned implementations. The problem is that getting high performance across different hardware is genuinely hard. NVIDIA's CUDA moat exists because writing fast kernels requires deep expertise. Most teams either accept vendor lock-in or hire expensive kernel engineers. Our goal is to break the CUDA moat. The compute bottleneck is the biggest constraint on AI progress. NVIDIA can't manufacture enough GPUs, and their monopoly keeps prices astronomical. Meanwhile, AMD, Google, and Amazon are shipping capable alternative hardware that nobody uses because the software is too hard. We're breaking that moat. If we succeed, anyone will be able to train state-of-the-art models without thinking past their PyTorch code.
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