Member of Technical Staff, GPU Compiler
About the role
Role within SF Tensor to build the fastest GPU compiler and related tooling (kernel optimizer and model foundry) to maximize compute performance for AI workloads. End-to-end involvement across MLIR/LLVM backend, codegen, and search-based optimization with focus on correctness proofs and enterprise-grade compiler infrastructure.
Responsibilities
- Build and extend MLIR dialects and passes to optimize training and inference workloads
- Work in the LLVM backend, below ptixas, on instruction selection, scheduling, register allocation and direct cubin emission and work on standing up equivalent depth on AMD, TPU and Trainium targets
- Expand our search-based compiler infrastructure, including agent- and RL-driven program search and the formal correctness proofs that make aggressive search safe
- Implement classic compiler optimizations tuned for large-scale training
- Create hybrid codegen paths for cases where direct MLIR lowering isn't practical
- Own testing, benchmarking and performance regression systems, including bit-identical hardware models
- Work closely with our research team and customer workloads to find optimization opportunities that matter
Qualifications
- Deep experience in compiler infrastructure (LLVM, MLIR or similar)
- Strong background in GPU architecture and low-level optimization (CUDA, ROCm or similar)
- Hands-on experience with at least one of: PTX/SASS, GCN/RDNA assembly or other GPU ISAs
- Familiarity with ML compiler stacks (XLA, TVM, Triton, torch.compiler or similar)
- Solid systems programming skills in C++ and/or Rust
- Proven track record of building production-grade compiler infrastructure
Skills
Benefits
- Meaningful equity and benefits

About SF Tensor
Infrastructure for AI labs to focus on research.
AI researchers should be pushing the boundaries of what's possible with new architectures and training methods. Instead, they waste weeks configuring cloud infrastructure, debugging distributed systems, and optimizing their GPU code. We know because we lived it: While training our own models across thousands of GPUs earlier this year, we spent more time fighting our infrastructure than doing actual research. That why we're building two things. First, Elastic Cloud: a managed platform that automatically finds the cheapest GPUs across all providers, handles spot instance preemption, and cuts compute costs by up to 80%. Second, automatic kernel optimization that makes training code run faster by modeling hardware topology, often beating hand-tuned implementations. The problem is that getting high performance across different hardware is genuinely hard. NVIDIA's CUDA moat exists because writing fast kernels requires deep expertise. Most teams either accept vendor lock-in or hire expensive kernel engineers. Our goal is to break the CUDA moat. The compute bottleneck is the biggest constraint on AI progress. NVIDIA can't manufacture enough GPUs, and their monopoly keeps prices astronomical. Meanwhile, AMD, Google, and Amazon are shipping capable alternative hardware that nobody uses because the software is too hard. We're breaking that moat. If we succeed, anyone will be able to train state-of-the-art models without thinking past their PyTorch code.
More open roles at SF Tensor
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- Member of Technical Staff, GPU Kernels1mo agoHybrid (San Francisco, CA) · Engineering
- Member of Technical Staff, Post-Training & Applied Research1mo agoSan Francisco · SF Tensor
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