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Senior SoC Architect, RAS

NVIDIA· Architect
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Hybrid (Santa Clara, CA), Hybrid (Austin, TX), Hybrid (Hillsboro, OR)$184k - $287.5k + equityFull-timePosted 1mo ago

About the role

Senior Hardware Architect for Tegra SoCs focused on Reliability, Availability, and Serviceability (RAS). Drive end-to-end RAS hardware architecture across CPUs, interconnects, memory systems, IOs, and platform components, from concept through production readiness, with emphasis on space- and radiation-aware design for high-reliability applications.

Responsibilities

  • Define and drive SoC-level RAS hardware architecture across CPUs, interconnects, memory systems, IOs, safety islands, firmware interfaces, and platform-level components.
  • Own RAS features from concept through architecture specification, micro-architecture alignment, RTL implementation support, design verification, silicon validation, debug, and production readiness.
  • Develop architectural requirements for fault detection, correction, containment, isolation, telemetry, error reporting, recovery, graceful degradation, serviceability, and diagnostic observability.
  • Work with design, verification, validation, firmware, software, and platform teams to ensure RAS features are implementable, verifiable, debuggable, and aligned with system-level requirements.
  • Understand broader SoC architecture and how RAS mechanisms interact with performance, power, reset flows, clocks, memory hierarchy, interconnect behavior, firmware-visible controls, and platform software.
  • Create hardware specifications, architectural requirements, error-handling flows, design guidance, test plans, and architectural models in SystemC, C/C++, Python, or other modeling environments.
  • Plan and review verification and validation strategies for RAS mechanisms, including error injection, recovery validation, coverage analysis, resiliency modeling, and cross-functional reviews.
  • Assist in failure analysis and silicon debug for lab, post-silicon, production, and field findings; develop diagnostic screens and localization methods for latent, intermittent, and environment-sensitive failures.
  • Apply RAS architecture principles to high-reliability deployment environments, including space- and radiation-aware use cases with single-event effects.
  • Follow industry standards and best practices related to RAS, functional safety, semiconductor reliability, debuggability, verification, validation, and silicon testing.
  • Patent novel hardware architecture techniques to improve system resiliency, observability, serviceability, and recovery.

Qualifications

  • MS or PhD in computer engineering, electrical engineering, or equivalent experience.
  • At least 8+ years of SoC architecture, design, verification, reliability, silicon validation, or related hardware development experience.
  • Strong understanding of RAS in the SoC context, including fault detection, correction, telemetry, recovery, and serviceability mechanisms.
  • Experience defining and driving hardware architecture features through the full development lifecycle (architecture definition, design implementation, verification planning, validation, debug, production readiness).
  • Strong understanding of overall SoC architecture and ability to reason across micro-architecture, full-chip integration, firmware interfaces, software-visible behavior, platform flows, and customer use cases.
  • Industry expertise in one or more SoC architecture areas such as RAS, safety, debug, clocks, resets, interconnects, memory controllers, IO technologies, platform integration, firmware-visible error handling, or diagnostic infrastructure.
  • Hands-on experience with design verification, silicon validation, fault injection, coverage analysis, resiliency modeling, diagnostic development, or reliability validation methodology.
  • Familiarity with radiation effects, space operation, or other high-reliability deployment environments.
  • Excellent analytical, written, and verbal interpersonal skills for collaboration across multiple teams.

Skills

Required:SoC architectureRAS (Reliability, Availability, Serviceability)SystemC, C/C++, Python modeling
Nice to have:Failure analysis and silicon debugSpace/Radiation-aware design

Benefits

  • Equity eligibility
  • Comprehensive benefits package (details available at benefits page)
Last updated Sep 4, 2026. Interested? Apply on the company site.

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