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Senior Mask Layout Design Engineer

NVIDIA· Engineer, Mask Design
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Taiwan, Hsinchu, Taiwan, TaipeiFull-timePosted 1mo ago

About the role

Senior Mask Layout Design Engineer responsible for physical layout of high-speed mixed-signal circuits in sub-micron CMOS technologies, collaborating with ASIC/mixed-signal teams, and participating in floor planning, custom layout, and verification.

Responsibilities

  • Perform physical layout for mixed-signal functions (PLL, high-speed SerDes, ADCs, ESD structures) in sub-micron CMOS technologies using Cadence tools.
  • Collaborate cross-functionally with ASIC and mixed-signal engineers to customize designs for integration in VLSI products.
  • Participate in floor planning, custom layout, and verification against design rules and schematics.

Qualifications

  • BSEE or equivalent experience.
  • Minimum of 5+ years proven experience in Mask and Layout Design.
  • Deep understanding of analog circuit layout concepts in submicron CMOS technologies.
  • Authority with Cadence custom circuit design tools—particularly Virtuoso.
  • Experience with verification tools such as Dracula, Hercules, Calibre, and Primeyield.
  • Ability to work effectively in a team, strong interpersonal skills, passion and positive energy.
  • Proficiency in scripting languages such as Perl, Python, SKILL, etc.
  • Knowledge of DRC and LVS checking flows, ability to customize decks.

Skills

Required:Analog circuit layoutCadence VirtuosoVerification toolsScripting
Last updated Sep 4, 2026. Interested? Apply on the company site.

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