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DPU Performance Validation Engineer

NVIDIA· Engineer, ASIC
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Hybrid (Israel, Yokneam), Hybrid (Israel, Tel Aviv)full-timePosted 1mo ago

About the role

DPU Performance Validation Engineer responsible for performance characterization, debug, and validation of NVIDIA DPU silicon across single-die and multi-die systems. Collaborates with Design, Verification, FW, and Architecture teams to ensure robust product development. Works in simulation and emulation environments with RTL-level debug, waveform analysis, and system-level performance root-cause analysis.

Responsibilities

  • Learn and analyze system-level operation of NVIDIA DPUs
  • Debug and root-cause performance issues in pre-silicon environments, across RTL, waveform traces, and multi-die system simulations
  • Collaborate closely with design, verification, architecture, and performance modeling teams to isolate and fix issues
  • Develop and improve validation methodologies for performance experiments and data collection
  • Automate repetitive debug and validation tasks to scale coverage and efficiency.

Qualifications

  • B.Sc. in Electrical Engineering, Computer Engineering, or equivalent
  • 3+ years of experience in ASIC development/validation
  • Strong background in ASIC debug, including reading RTL, analyzing waveforms, and root-causing functional or performance issues
  • Hands-on experience with performance validation and analysis at the system level (die-level or multi-die systems)
  • Proficiency with Python and C/C++ in a Linux environment
  • Excellent interpersonal skills and ability to work as part of a multi-functional team.

Skills

Required:RTL debuggingsystem-level performance validationPythonC/C++
Last updated Sep 4, 2026. Interested? Apply on the company site.

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