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Full Chip CAD Physical Design Engineer

Google
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Tel Aviv, Israel; Haifa, IsraelFull-timePosted 1mo ago

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions powering Google's direct-to-consumer products. Focuses on RTL to GDS II flow, large complex SoCs, and advanced node design within Google’s AI and Infrastructure initiatives.

Responsibilities

  • Demonstrate an understanding of the RTL to GDS II flow.
  • Manage the implementation of large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, and address related issues and solutions.
  • Utilize floorplanning, power grid design, and place-and-route methodologies, and use Synopsys tools like Floorplan Compiler (FC) and Formality.
  • Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
  • Develop scripts in Synopsys TCL and Python.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
  • 10 years of experience in electronic design automation (EDA) tools and RTL2GDS flows.
  • Experience in the semiconductor/EDA industry.

Skills

Required:RTL to GDS II flowSoC/Systems integrationfloorplanning and power grid designSynopsys tools (FC, Formality)advanced node design (5nm and below)Scripting (TCL, Python)
Last updated Oct 23, 2026. Interested? Apply on the company site.

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