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SoC Design Verification Engineer

Google
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Tel Aviv; HaifaFull-timePosted 1mo ago

About the role

Be part of a team that pushes boundaries, developing custom silicon solutions that power Google's direct-to-consumer products. You will verify digital designs as part of a server chip design team, building verification components, constrained-random testing, system testing, and driving verification closure for Google's SoC projects.

Responsibilities

  • Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
  • Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM), or formally verify designs with SystemVerilog Assertion (SVA) and industry leading formal tools.
  • Identify and write all types of coverage measures for corner-cases.
  • Debug tests with design engineers to deliver functionally correct design blocks.
  • Close coverage measures to identify verification holes and to show progress towards tape-out.

Qualifications

  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
  • 4 years of experience with creating and using verification components and environments in standard verification methodology.
  • Experience verifying digital systems using standard IP components/interconnects (microprocessor cores, hierarchical memory subsystems).
  • Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for FPGAs or ASICs.

Skills

Required:SystemVerilogUniversal Verification Methodology (UVM)Constrained-random verificationDebugging
Nice to have:Formal verification
Last updated Oct 23, 2026. Interested? Apply on the company site.

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