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Senior AI SoC Modeling Engineer

Amazon· Annapurna Labs Machine Learning Accelerators, AWS
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Hybrid (Cupertino, CA / Austin, TX)$168.1k - $227.4kFull-timePosted 1mo ago

About the role

Model high-fidelity C++/SystemC representations of AWS AI/ML accelerators and SoCs (Trainium/Inferentia), validate against RTL/silicon, and collaborate across design, verification, and software teams to influence architecture and silicon strategy.

Responsibilities

  • Develop and maintain high-fidelity functional model of AI/ML accelerator and its SoC subsystems, including compute engines, memory hierarchies, on-chip interconnects, and data paths — translating architecture specs and RTL behavior into accurate, testable C++ models
  • Validate model behavior against RTL simulations, emulation platforms, or silicon measurements; debug discrepancies and drive model-to-RTL correlation to high fidelity
  • Partner with design verification teams to integrate models into pre-silicon validation environments and catch architectural bugs early in the design cycle
  • Collaborate with architects/micro-architects, RTL design engineers, ML SW engineers, and compiler engineers to evaluate architecture and microarchitecture tradeoffs and help make hardware design decisions
  • Contribute to cycle-approximate performance model effort enabling architectural exploration ahead of RTL availability, early software development
  • Quantify system-level tradeoffs across compute, memory bandwidth, networking, and storage to influence reference architectures and long-term silicon strategy
  • Build and improve modeling infrastructure: simulation frameworks, regression suites, automated correlation checks, and coverage-driven validation flows
  • Develop modeling methodologies and tools that scale across multiple IP blocks and SoC generations, improving team efficiency and model reuse
  • Your models are used to verify silicon before it's built — enabling early bug detection and significant savings
  • Work at the intersection of software engineering and chip design with visibility into ML accelerators
  • Opportunity to evolve into architectural modeling and influence chip design decisions
  • Operate in a small, high-ownership team with direct impact on AWS silicon programs
  • No ML background required; domain learning on the job after joining

Qualifications

  • 6+ years of full software development life cycle, including coding standards, code reviews, source control management, build processes, testing, and operations experience
  • Experience as a mentor, tech lead or leading an engineering team
  • 6+ years writing functional or performance models of hardware (SoCs, ASICs, GPUs, CPUs, IP blocks)
  • Experience programming in C++, using advanced language features
  • Knowledge of SoC, CPU, GPU, and/or ASIC architecture and micro-architecture

Skills

Required:Functional or performance modeling of hardwareC++ programming
Nice to have:SystemC or cycle-approximate modelingDV/test integrationRTL correlationRegression/CI for model validationMultithreading/distributed simulationModern C++ML accelerator architecture knowledgeArchitectural modeling
Last updated Oct 25, 2026. Interested? Apply on the company site.

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