ASIC Design Engineer – Clocks IP
NVIDIA· Engineer, ASIC
Santa Clara, CA / Austin, TX$116k - $189.8kfull-timePosted 1mo ago
About the role
Clocks team ASIC engineer to architect clock domains for GPU/CPU, collaborates across design, physical, verification, and silicon bring-up to optimize PPA and deliver clocking RTL for GPUs/CPUs/SOC.
Responsibilities
- As a Clocks team member, you will be architecting the clock domain to satisfy functional, physical and testing design requirements.
- Engage with multiple teams and design the GPU or CPU clocks to satisfy all the architectural/design/physical constraints.
- Improve Power, Performance, and Area (PPA) of innovative NVIDIA chips by evaluating trade-offs across DFx, Physical Implementation, Power Optimization and Ease of timing closure to innovate and implement new Clocking topologies in RTL.
- Collaborate with Physical design and timing team to evaluate Clocking concerns and develop solutions for supporting high speed Clocking.
- Together with other team members, we deliver clock RTL information to GPU, CPU and SOC verification team, timing and DFT teams.
- Get involved in end-to-end cycle of ASIC execution starting from micro-arch, design implementation, design fixes, sign-off checks and all the way to Silicon bringup.
Qualifications
- BS in Electrical Engineering or equivalent experience (MS preferred)
- 2+ years of relevant work experience.
- Deep understanding of logic optimization techniques and PPA trade-offs.
- Excellent interpersonal skills and ability to collaborate with multiple teams.
- Experience in RTL design (Verilog), verification and logic synthesis.
- Strong coding skills in python or other industry-standard scripting languages.
- Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus.
- Implementing on-chip clocking networks is a bonus
Skills
Required:RTL design (Verilog)VerificationLogic synthesisPython scripting
Benefits
- equity
- benefits
Last updated Oct 23, 2026. Interested? Apply on the company site.
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